PARALLEL MATRIX MULTIPLICATION CIRCUITS FOR USE IN KALMAN FILTERING

In this work we propose several ways of the CMOS implementation of a circuit for the multiplication of matrices. We mainly focus on parallel and asynchronous solutions, however serial and mixed approaches are also discussed for the comparison. Practical applications are the motivation behind our investigations. They include fast Kalman filtering commonly used in automotive active safety functions, for example. In such filters, numerous time-consuming operations on matrices are performed. An additional problem is the growing amount of data to be processed. It results from the growing number of sensors in the vehicle as fully autonomous driving is developed. Software solutions may prove themselves to be insuffucient in the nearest future. That is why hardware coprocessors are in the area of our interests as they could take over some of the most time-consuming operations. The paper presents possible solutions, tailored to specific problems (sizes of multiplied matrices, number of bits in signals, etc.). The estimates of the performance made on the basis of selected simulation and measurement results show that multiplication of 3×3 matrices with data rate of 20 100 MSps is achievable in the CMOS 130 nm technology

A Flexible, Low-Power, Programmable Unsupervised Neural Network Based on Microcontrollers for Medical Applications

We present an implementation and laboratory tests of a winner takes all (WTA) artificial neural network (NN) on two microcontrollers (μC) with the ARM Cortex M3 and the AVR cores. The prospective application of this device is in wireless body sensor network (WBSN) in an on-line analysis of electrocardiograph (ECG) and electromyograph (EMG) biomedical signals. The proposed device will be used as a base station in the WBSN, acquiring and analysing the signals from the sensors placed on the human body. The proposed system is equiped with an analog-todigital converter (ADC), and allows for multi-channel acquisition of analog signals, preprocessing (filtering) and further analysis

Current Mode Euclidean Distance Calculation Circuit for Kohonen's Neural Network Implemented in CMOS 0.18μm Technology

In this paper we present analog current mode Euclidean distance calculation (EDC) block, which calculates the distance between two current vectors. The proposed circuit is an important part of the CMOS-implemented Kohonen’s neural network (KNN) designed for medical applications. The input data vector is compared with the weights’ vector in each neuron in proposed KNN. The neuron, whose weights are the closest to the input training vector becomes the winner and in the next step changes its weights. Proposed EDC block performs several operations such as: subtraction, squaring and summing of the current signals. The output current is the exact measure of the Euclidean distance. Proposed circuit dissipates power 15 μW from 1.5 V voltage supply, working with 20 MHz input data frequency. The signal frequency as well as the power dissipation may be scaled down to 1 MHz and 300 nA. Proposed EDC circuit, in CMOS 0.18 μm technology, occupies area about 500 μm2

Flexible and Low Power Binary-Tree Current Mode Min/Max Nonlinear Filters Realized in CMOS Technology

In this paper we present current mode, programmable, binary tree MIN/MAX filters designed for nonlinear data processing. Proposed circuits can be used in image filtration, to realize operations such as erosion or dilatation that are useful in noise reduction or correction of objects in the images. Two kinds of filters are proposed. The first one has been designed for 1-dimensional (1-D) signal processing. Samples of the input signal are being stored in the circular analog delay line. Each sample remains on its fixed position in the delay line as long as is overwritten by the new sample after number of clock phases that is equal to the filter order N. As a result, only one analog delay element is updated with every new signal sample. This minimizes both the power dissipation and errors that in other types of filter structures are associated with data rewriting. The 2-D filters proposed in this paper are the natural extension of 1-D filters. These filters have been realized as universal 2-D structures, which can be easily reprogrammed to perform various nonlinear operations. The experimental 2-D image processor with 64 inputs (8x8 cluster) has been designed in CMOS 0.18um technology and successfully tested in HSPICE simulations. Designed circuit enables parallel calculation of 64 pixels with the rate that is equal to 500 thousands image frames per second, dissipating power about 20 uW. Resultant data rate is therefore equal to 32 MSamples/s and energy consumed per one calculated pixel is about 1 pJ

A Low Power Current-Mode Binary-Tree WTA / LTA Circuit for Kohonen Neural Networks

A novel current-mode, binary-tree WTA / LTA circuit for application in analog Kohonen neural networks has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure that allows to determine either the Min or the Max signal, depending on the configuration. The circuit realized in the TSMC CMOS 0.18 μm process offers a precision of about 99 % at the data rate of 3.5 MSps and energy consumption of about 0.7 pJ per one input signal per cycle

Influence of Information Leakage in Analog Memory on Learning Kohonen Network on Silicon

The paper presents an influence of leakage effect observed in capacitive analog memories on learning process in hardware implemented Kohonen neural networks with MOS transistors used as switches connected with information holding capacitors. The learning results, i.e. variations (adaptations) of weight values, strongly depend on the transistor leakage currents. This is a cause for some quantization error associated with the weight adaptations during the network training. The unwanted leakage influence can be minimized in several ways discussed in this paper. As expected, the observed leakage influence on the memory storage time rises with an increase of temperature. This has been verified by means of computer simulations (Matlab, HSpice) as well as measurements of a prototyped Kohonen network chip (0.18 mu m CMOS process)

Adaptive Weight Change Mechanism for Kohonens's Neural Network Implemented in CMOS 0.18 μm Technology

In this paper, we present a block of adaptive weight change (AWC) mechanism for analog current-mode Kohonen's Neural Network (KNN) implemented in CMOS 0.18 μm technology. As some other essential building blocks of KNNs dealing with the calculations of the Euclidean distance, formation of a conscience mechanism and a determination of the winner-takes-all (WTA) circuits have been already developed, the AWC forms another essential step towards the realization of the network. We show that the proposed network works with small values of analog signals thus resulting in low power dissipation and chip area when compared with digital realizations of KNNs. Each neuron occupies chip area equal to about 1000 μm2 and dissipates 20 μW of power for 20 MHz input data rate

0.35 μm 22μW Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications

The paper presents the programmable multiphase clock generator for switched-capacitor finite impulse response (SC FIR) circular memory filters. The proposed programmable clock circuit enables easy division of such kind of filters into different orders smaller sections, which when connected in series, lead to increase in filter efficiency: reduction of chip area, power dissipation, and rising up of the speed. The proposed clock generator enables adjustment of the impulses width, that simplifies design process and leads to structure, which is more robust to process variation. The clock circuit realized in CMOS 0.35μm technology, dissipates 22 μW from 2 V power supply

CMOS Implementation of Low Power Kohonen’s Neural Network for Medical Applications

Recently, artificial intelligence (AI) systems gain an increasing popularity and their development is fast. One of the most important fields of the AI system development are artificial neural networks (ANN’s) which, due to continuous progress in microelectronics and integrated circuits (IC) manufacturing, can be realized as large integrated blocks. Designers of such IC ANN’s take inspiration from biological networks. Networks of this type operate with analog signals, include a big number of neurons and a still bigger number of interconnections between them and, as a result, are able to process the information in parallel on a large scale. Recent advances in digital CMOS technologies enable implementation of different analog circuits in a VLSI integrated circuit form. The design and optimization efforts go towards reducing power dissipation, which is especially important in various diagnostic applications

Experimental Kohonen Neural Network Implemented in CMOS 0.18μm Technology

In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been realized using building blocks proposed earlier by the authors, such as binary tree current-mode winner takes all (WTA) circuit, Euclidean distance calculation circuit (EDC), adaptive weight change mechanism (AWC), conscience mechanism (CONS), initial weight initialization mechanism (IB). The network performance has been verified in the way of measurements. The obtained measurement results are in a good agreement with theoretical considerations as well as HSPICE simulations. The circuit occupies a chip area (without pads) equal to 0.07 mm2 and consumes 1 mW of power for 1.8 V supply. The input currents are in the range between 1 and 7 μA. We intend to apply the designed KNN to analyze ECG biomedical signals